1. Field of the Invention
The present invention generally relates to plasma display apparatuses, and particularly relates to a plasma display apparatus that displays images by generating discharge between electrodes.
2. Description of the Related Art
Plasma display panels have two glass plates on which electrodes are formed, and discharge-purpose gas fills the gap between the two glass plates that is in the order of 100 microns. Voltages higher than a discharge threshold voltage are applied between the electrodes to start gas discharge, and ultraviolet light generated from the discharge induces the light emission of photo florescent provided on the plate, thereby effecting screen displaying.
FIG. 1 is a diagram showing a schematic construction of a plasma display apparatus.
A display panel 10 includes X electrodes 11 and Y electrodes 12 disposed in parallel, and further includes address electrodes 13 disposed in perpendicular thereto. The X electrodes 11 and the Y electrodes 12 are used to provide sustain discharge for display-purpose light emission. Voltage pulses are applied between the X electrodes 11 and the Y electrodes 12, thereby carrying out sustain discharge. Further, the Y electrodes 12 serve as scan-purpose electrodes for writing display data. The address electrodes 13 are used to select display cells 15 that are to emit light. A voltage for writing discharge is applied between the Y electrodes 12 and the address electrodes 13 so as to select discharge cells. Shields 14 are provided between the address electrodes 13 for the purpose of separating the discharge cells 15.
Discharge in the plasma display panel can only assume either one of the “on” state and the “off” state, so that the density, i.e., the gray scale, is represented by the number of repeated light emissions. To this end, a frame is divided into 10 sub-fields, for example. Each sub-field is comprised of a reset period, an addressing period, and a sustain discharge period. During the reset period, all cells are equally initialized regardless of lighting status in the previous sub-fields, e.g., are placed in the condition in which wall charge is erased. During the addressing period, selective discharge (addressing discharge) is performed to select the on/off state of cells in accordance with display data, thereby selectively generating wall charge that places cells in the “on” state. During the sustain discharge period, discharge is repeated in the cells where addressing discharge was performed to generate wall discharge, thereby emitting light. The length of the sustain discharge period, i.e., the number of repeated light emissions, differs from sub-field to sub-field. For example, the ratio of the numbers of light emissions from the first sub-field to the tenth sub-field are set to 1:2:4:8: . . . :512, respectively. Sub-fields are then selected in accordance with the luminance level of a display cell to be subjected to gas discharge, thereby achieving a desired gray scale level.
FIG. 2 is a drawing for explaining another construction of a display panel unit different from that of FIG. 1.
In a display panel unit 10A of FIG. 2, X electrodes 11A and Y electrodes 12A serving as display electrodes are provided in turn at equal intervals so as to cross address electrodes 13A. All gaps between the electrodes are utilized as display lines (L1, L2, . . . ). This configuration is called an ALIS (alternate lightning of surfaces) method (Patent Document 1). Since all the gaps between the electrodes are utilized as display lines, the number of electrodes is half as many as that of FIG. 1, which provides a basis for cost reduction and scale reduction.
Since all the gaps between electrodes serve as display lines in the ALIS method, it is impossible to light up all the display lines simultaneously. Lighting of odd-number lines (L1, L3, . . . ) and lighting of even-number lines (L2, L4, . . . ) are temporally separated to effect displaying. In the ALIS method, One frame is divided into two fields, each of which is comprised of a plurality of sub-fields. The first field is used for the displaying of odd-number lines, and the second field is used for the displaying of even-number lines.
FIG. 3 is a drawing showing the construction of a plasma display apparatus.
The plasma display apparatus of FIG. 3 includes a plasma display panel 20, a Y electrode drive circuit 21, an X electrode drive circuit 22, an address electrode drive circuit 23, a discrimination decision circuit 24, a memory 25, a control circuit 26, and a scanning circuit 27.
A vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock signal Clock, and RGB signals each comprised of 8 bits and serving as data signals are supplied to the discrimination decision circuit 24. The discrimination decision circuit 24 writes RGB data in the memory 25 as display data in response to the vertical synchronizing signal Vsync. The control circuit 26 controls the Y electrode drive circuit 21, the X electrode drive circuit 22, the address electrode drive circuit 23, and the scanning circuit 27, and displays the display data stored in the memory 25 on the plasma display panel 20. In conjunction with this, the scanning circuit 27 scans the Y electrodes Y1 through Yn, and the address electrode drive circuit 23 drives the address electrodes A1 through An, thereby together effecting writing electric discharge for writing data in the plasma display panel 20. In the display cells where data were written, further, sustain electric discharge is generated between the Y electrodes Y1 through Yn and the X electrodes X1 through Xn by the Y electrode drive circuit 21 and the X electrode drive circuit 22.
In the related-art construction shown in FIG. 3, lines y1 through yn that extend from the Y electrode drive circuit 21 to the scanning circuit 27 to be connected to the Y electrodes Y1 through Yn take different wiring paths between the Y electrode drive circuit 21 and the scanning circuit 27, so that they have different wire lengths. Likewise, the X electrodes X1 through Xn extending from the X electrode drive circuit 22 to the plasma display panel 20 take different wiring paths to have different wire lengths. In the example of FIG. 3, for example, the line y1 and the Y electrode Y1 connected thereto both having long wiring lengths have wiring resistance and wiring inductance larger than those of the line y3 and the Y electrode Y3 connected thereto both having relatively short wiring lengths. By the same token, the X electrode X1 having a long wiring length has wiring resistance and wiring inductance larger than those of the X electrode X3 having a relatively short wiring length. An effect of the wiring inductance is especially strong. Because of this, when an electric current runs through wiring lines and electrodes to generate electric discharge between the Y electrodes Y1 through Yn and the X electrodes X1 through Xn, a voltage drop occurs along the wiring lines and electrodes. The voltage drop generated in this manner differs from wiring line to wiring line and from electrode to electrode
As a result of this voltage drop, when a sufficient margin cannot be secured for the discharge voltage of the plasma display panel with respect to the electrodes having a large voltage drop, a sufficient voltage required to light up an electric discharge may not be supplied. In such a case, a flicker of a screen or the like will appear, thereby degrading display quality.
In order to address a drop in the operation margin, a conductive plate layer is disposed such as to overlay the wiring lines, providing a voltage fluctuation balancing unit, which reduces the variation of voltage drops by eddy currents that occur in the conductive plate layer in response to electric currents running through the wiring lines (Patent Document 2). This method can suppress the variation of voltage drops that occur according to the length of individual wiring lines, and can increase the operation margin.
Patent Document 1                Japanese Patent No. 2801893        
Patent Document 2                Japanese Patent Application Publication No. 2002-196719        
FIG. 4 is an illustrative drawing showing a related-art X electrode drive circuit (or Y electrode drive circuit) as implemented on a printed circuit board.
The construction of FIG. 4 includes a printed circuit board 30, a sustain outputting pattern 31, sustain power supply capacitors 32A and 32B, sustain circuits 33A and 33B, electric power collecting capacitors 34A and 34B, electric power collecting coils 35A and 35B, ground screws 36A and 36B, and connectors 37A and 37B. The sustain circuit 33A is provided with the sustain power supply capacitor 32A, the electric power collecting capacitor 34A, a sustain power supply terminal 41A for connection with the electric power collecting coil 35A, a sustain outputting terminal 42A for connection with the sustain outputting pattern 31, and a sustain grand terminal 43A for connection with the ground screw 36A. Likewise, the sustain circuit 33B is provided with the sustain power supply capacitor 32B, the electric power collecting capacitor 34B, a sustain power supply terminal 41B for connection with the electric power collecting coil 35B, a sustain outputting terminal 42B for connection with the sustain outputting pattern 31, and a sustain grand terminal 43B for connection with the ground screw 36B.
The sustain outputting pattern 31 is a single metal plate, and serves as a conductor that supplies discharge currents (i.e., currents that run through X electrodes and Y electrodes during the sustain discharge period) from the sustain circuits 33A and 33B to the connectors 37A and 37B.
In the X electrode drive circuit (or the Y electrode drive circuit) shown in FIG. 4, the sustain circuits 33A and 33B are provided in parallel, and are together connected to the sustain outputting pattern 31 in order to secure a sufficient sustain discharge current that is supplied to the X electrodes X1 through Xn of FIG. 3 (or the Y electrodes Y1 through Yn of FIG. 3). These two sustain circuits 33A and 33B have such construction that circuit components are shifted in parallel from the upper side to the lower side across the center line of the printed circuit board shown by a dashed line.
Such arrangement of circuit components provides for design to be simplified by using the substantially same component arrangement and wiring patterns on the upper side and the lower side for the two sustain circuits 33A and 33B which are connected in parallel. Further, when a hybrid IC or a power module is used for the sustain circuits 33A and 33B, the two sustain circuits can be consolidated, resulting in the reduction of the number of circuit components.
When the construction of the printed circuit board shown in FIG. 4 is used, however, current paths extending from the sustain outputting terminals 42A and 42B to the connectors 37A and 37B differ for each terminal in the connector. Because of this, wiring resistance and wiring inductance differ for each terminal, resulting in voltage variation at the terminals being different depending on the position of terminals when sustain discharge currents flow. Consequently, a problem arises in that the operation margin of a sustain voltage drops in the plasma display apparatus.
The use of the voltage fluctuation balancing unit shown in the above-described Patent Document 2 may provide a proper measure against the drop of the operation margin. However, there is no related-art technology that teaches a specific construction of a printed circuit board.
Accordingly, there is a need for a plasma display apparatus that has an improved characteristic in the fluctuation of voltage drops, which are caused by differences in the length of current paths on a printed circuit board.